The MFSK FEC Coder

Ver 1.0, 11 July 2000

Grateful thanks to Phil KA9Q for the algorithms and Viterbi decoder routines. Check the KA9Q web site for lots of good stuff on coders and decoders.

The MFSK FEC coder (also used in the IZ8BLY PSK63F program) consists of a sequential convolutional coder of Rate R = 1/2, with a Constraint Length K = 7.

Therefore, for every input data bit there are two output data "dibits", generated by two polynomials from the taps of a 7 stage shift register. Call the outputs of these registers O₁ to O₇. The polynomials are each the modulo 2 sum (XOR) of five of these register outputs. The polynomials are:

Dibit₁ = O₁ + O₃ + O₄ + O₆ + O₇
Dibit₂ = O₁ + O₂ + O₃ + O₄ + O₇

The dibits defined above are multiplexed into a single data stream, in order Dibit₁ then Dibit₂. They are then transmitted sequentially in a data stream that is coded by bit weight into MFSK symbols, with the first arriving bit given maximum weight. No specific fixed bit weight is given to either dibit, which would allow easy identification at the receiver decoder. Thus the bit weight of each dibit is uncertain; all that can be said is that in the resulting bit stream at the receiver, Dibit₁ precedes Dibit₂.

The reason for this approach is flexibility: this technology is intended for anywhere from 1 to 5 or more bits per symbol.

The FEC decoder is of the Viterbi type. As mentioned, there is no fixed relationship between the coder dibits and the bit weighting of the MFSK symbol (or the PSK63F dibits, which are on the same data stream), and so the decoder must decide from the results whether it has the correct order of dibits. There are two choices - Dibit₁ then Dibit₂ (correct), or Dibit₂ of one bit then Dibit₁ of the next (incorrect).

One technique for solving this ambiguity is to use two short "trial decoders" and use the metrics from these to decide which of the two ambiguous alternatives gives the best result, and therefore the order in which the dibits must be used for the full-length decoder.

The FEC coder is followed (in MFSK only) by an interleaver. See the Interleaver Description for details. The interleaver is a simple diagonal 10 stage concatenated n-bit interleaver, where n is the number of bits represented by the MFSK symbol.