GPL Telephony Hardware

This page describes line interface hardware being developed for the project by a growing number of contributors. There are now several hardware development projects under way, covering the entire range of line interface hardware types. The best part is that all of the designs are open - you are free to use them for your hardware project!

1. Four Port FXO: A daughter board for the BF533 STAMP called 4fxo (four-eff-X-Oh) that contains (you guessed it) four FXO ports. It also has a SD-card to provide extra flash storage required to implement the target IP-PBX application. This design has been prototyped and driver development and debugging is under way.

2. E1/T1 Primary Rate: a daughter board for the BF533 STAMP called pr that contains a single span E1/T1/J1 interface. Like the 4fxo design, it also has a SD-card interface providing extra flash. This project is in the schematic layout stage. If anyone would like to champion this project please contact me. It won't take much effort (a few weeks) to finish the schematic and layout the PCB as this design is quite simple. I am happy to fund the parts and PCB fabrication costs if anyone is interested in completing the hardware design.

3. Four Port Basic Rate ISDN: The Fourfin project is a 4 port (8 channel) BRI card for the STAMP. A schematic and PCB has been designed, and the driver is being developed with the use of an evaluation card.

4. 2 FXS/2 FXO: Jerry Zeng from Analog Devices is working on both a four port FXS and an 2 FXS/2 FXO daughter card for the STAMP. Initial schematics for the 4 port FXS card are here. The prototype hardware has been built, FXS and FXO hardware has been debugged and tested. Phone calls have been made using this hardware and uCasterisk! Further driver integration and optimisation is under way.

1. Four Port FXO/FXS: A four port daughter card for the STAMP - with pluggable FXS/FXO modules and SD-card to provide extra flash storage. Current status is all three PCBs have been fabricated and are currently being loaded. The design is easily expandable to 8 or 12 ports. More information here.

2. BlackfinOne: A low cost BF532 Blackfin mother board. A new version is being developed with dual Ethernet ports and USB to support the telephony daughter boards described above. More information here.

Some possible applications:

1. By combining a BF533 STAMP board, a daughter board, uCasterisk, and some IP handsets you can make a low cost powerful IP-PBX suitable for home or small business.

2. The STAMP/daughter-board combination can be used as a line interface solution as an alternative to a PCI card mounted in a PC. You can then connect via Ethernet to a host PC running the actual telephony application software.

3. By customising the software on the STAMP, low volume custom telephony applications (for example a SIP voice mail system or a stand alone embedded voice logger) can be developed. You can even modify the hardware if you like, as it is GPL.

In December 2005 I expressed an interest in building a range of line interface hardware cards for the Blackfin. A key point was to make the designs GPL, like the Blackfin STAMP hardware. This means anyone is free to copy and build on the hardware designs.

Since then the project has started taking off with several contributors from around the world developing a range of line interface hardware (and now a custom Blackfin motherboard).

Why GPL hardware? Well Robin Getz from the STAMP team explains it better than I can here.

I have also blogged on Open Source Hardware here.

In the near future I intend to get the Blackfin/line interface hardware combination compliance tested and approved. This is required for legal connection to the telephone lines.

We would welcome any help from anyone who is interested, for example drivers, hardware, testing, Asterisk configuration. The only line interface not under active development is the PR E1/T1 project - we would especially welcome some help there.

As a starting point I have connected a Digium X100M module to a BF533 STAMP card. This module is a single port FXO card (i.e. it connects to telephone lines) that usually sits on a 4 port Digium PCI card.

The X100M card uses the Silicon Labs 3050 chip. The chip is very low cost (around US$5 each). Data is available from the Silicon Labs site.

I have ported the GPL wcfxs.c driver (part of the Asterisk zaptel package) to the Blackfin, and can make phone calls over the FXO interface (e.g. FXO to SIP). This driver talks to the 3050 chip (and it's FXS equivalent). To test the system I drive the FXO port from an analogue PBX (actually a PC based Asterisk system). The load average during a call was only 0.07, however I guess top doesn't include the kernel mode driver that is performing the echo cancellation.

Some screen shots of the X100M connected to a Blackfin STAMP are here and here .

I soldered the cards together to avoid any high speed digital problems - the Blackfin edge rates are very fast and there are very few grounds on the SPORT and PF connectors so I wanted to keep lines as short as possible.

Here is a screen shot showing the modules loading on a BF533 STAMP board:

 _   _| |  | | _ ____  _   _ \ \/ /
| | | | |  | || |  _ \| | | | \  /
| |_| | |__| || | | | | |_| | /  \
|  ___\____|_||_|_| |_|\____|/_/\_\
|_|

For further information see:
http://www.uclinux.org/
http://blackfin.uclinux.org/



BusyBox v1.0e (2005.10.03-00:27+0000) Built-in shell (msh)
Enter 'help' for a list of built-in commands.

th0: link down
root:~> eth0: link up, 100Mbps, full-duplex, lpa 0x45E1
cd /var/tmp
root:/var/tmp> insmod zaptel.ko
Zapata Telephony Interface Registered on major 196
root:/var/tmp> insmod wcfxs.ko
Module 0: Installed -- AUTO FXO (FCC mode)
Found a Wildcard TDM: Blackfin STAMP (1 modules)
root:/var/tmp>

The 4fxo card is the first daughter card design for the BF533. A schematic and PCB for the 4fxo card has been designed (download here) and the next step is prototype fabrication.

Here is the PCB layout of one of the four FXO ports, inside the PCB editor:

Some features of the card:

1. Four FXO ports designed for world-wide compliance based on the 3050/3019 Silicon Labs chip set.

2. This chip set is already well supported by Asterisk in the wcfxs.c zaptel driver. This driver has been ported to the Blackfin.

3. An SD-card interface to allow the flash memory storage of the STAMP to be expanded from the default 4MB. This will provide the system with enough memory to store all of the files (e.g. uCasterisk image, voice prompts) required for a full feature IP-PBX. The SD-card connects via the serial SPI port which should allow up to 2MB/s transfer rate. Alternatively the STAMP already has plenty of SDRAM, so at boot time files can be copied from the SD-card to SDRAM.

4. A clock oscillator to provide the 2.048MHz PCLK required for the Si3050 chips. Unfortunately the STAMP cannot generate the clock we need using the internal dividers as the master clock frequency doesn't divide down neatly. An alternative here is to re-crystal the STAMP.

5. The card mounts on top of the BF533 STAMP, and plugs into the SPORT0 connector. It is secured by screws on stand-offs.

The schematic is organised on two levels. The top level schematic is called 4fxo.sch. It represents the hardware for each FXO port as a FXO component. The file fxo.sch contains the (identical) circuit that is used for each FXO port. This two level arrangement lets us use only 2 sheets rather than 5, and simplifies and changes, you only have to change the fxo.sch sheet to make changes on all 4 ports. It also makes it easy to change the design to support different configurations, for example 2 FXS and 2 FXO ports.

The 4fxo design has two serial busses:

1. The SPI bus is used for control of the Si3050 chip set and access to the SD-card. The SPI bus is only clocked when data needs to be transferred (e.g. polling for ring detection, or taking a port off hook, reading the SD-card). There are two Chip Selects (CS), one for the SD-card, and one for all four FXO modules. The 4 FXO modules are daisy chained as described in the Si3050 data sheet and therefore only require one CS line for all four devices.

2. The TDM bus transfers voice data (speech samples) at a constant rate between the Si3050 chips and the BF533. It is clocked at 2.048MHz, and the sample rate is 8KHz.

The signals from the STAMP have been series terminated and buffered (U2) to allow a fine degree of control over the edge rates on signals on the board. The STAMP signals are very fast (1ns or so) and there are very few grounds on the SPORT0 connector so I want to be conservative here. The buffer (U2) means the high speed signals from the STAMP have the minimum length (U2 should be placed as near as the SPORT connector J5 as possible). The currents therefore travel in a small loop which minimises inductance and radiation (helping us pass EMI compliance).

Remaining Tasks are:

1. SD card driver development and testing (see here for more details. This could be initially prototyped without the 4fxo PCB, as you only need to connect 7 wires between the STAMP and the SD-card. A nice mini-project for some one?

2. Modification of the wcfxs.c driver to support 4 FXO ports.

3. Integrate and test with uCasterisk.

4. Compliance testing.

Please let me know if you would like to help with any of these tasks.

References

The design for each port is straight out of the Si3050 data sheet and Si3050PPT-EVB Evaluation Board document.

From the Silicon Labs site check out:

1. Si3050 data sheet

2. Si3050PPT-EVB Evaluation Board documentation.

3. AN67 Layout Guidelines (Si3050PPT-EVB also has a sample layout)

Also:

1. wcfxs.c from the ucasterisk tar ball.

2. SD Card Interfacing from the OpenWRT project Wiki.

Design Rule Check

The gnetlist tool from the geda package was used to Design Rule Check (DRC) the 4fxo design, currently there are no DRC errors. The tiny nc components are dummy components that I connect to not-connected pins. This helps remind me that I have considered this pin and decided to leave it unconnected. It also keeps the DRC checker from issuing errors.

[david@solomon 4fxo-0.1]$ gnetlist -g drc2 -o - 4fxo.sch
Loading schematic [/home/david/4fxo-0.1/4fxo.sch]
Checking non-numbered parts...

Checking duplicated references...

Checking nets with only one connection...

Checking type of pins connected to a net...

Checking unconnected pins...

Checking slots...

Checking duplicated slots...

Checking unused slots...

No warnings found.
No errors found.
[david@solomon 4fxo-0.1]$

The pr card is the second daughter card design for the BF533. The pr card is currently in the design stage, a schematic is available. Next steps include completing the schematic, PCB layout and prototype fabrication.

The heart of the design is the Infineon 2256 (aka FALC56) "E1/T1/J1 Framer and Line Interface" chip. This chip was chosen as it is already used on hardware supported by Asterisk (Digium TDM110 card) and has an existing driver (zaptel wcte11xp.c). The intention is to port this driver by replacing the PCI interface code with code to interface to the Blackfin, as per the X100M hack above.

I have designed quite a few FXO/FXS cards before but haven't done any work on primary rate cards. So this card means climbing a steep learning curve for me. Which makes it lots of fun :-) I would appreciate any advice or comments from the more experienced E1/T1 gurus out there!

Curiously (to me at least), this card is actually much simpler than the analog 4fxo card, at least in parts count.

Design Notes

The pr card has two busses; a TDM bus to transfer voice data, and a parallel bus used for control and configuration data.

The parallel bus is designed to be memory mapped into a micro-controllers address and data bus. I have constructed a bit bashed version of a parallel bus using the STAMP PPI connector and the PF pins. Bit bashed means that the driver will manually have to configure all the control signals, e.g. assert ALE, de-assert it and assert nRD. Pretty ugly I know. The reason I have done it this way was so that the the pr card can plug straight into a standard BF533 STAMP, using the SPORT0 and PPI connectors.

The alternative is to connect the parallel interface to the Blackfins address/data bus. This is possible, but requires soldering connectors onto the back of the STAMP, and mounting the pr card on the back of the STAMP. So this approach is harder for the sort of low volume production I would like to set up first so that people can start experimenting with the pr card connected to a STAMP. I am assuming that most people would rather a daughter card that plugs straight in rather than having to perform open heart surgery (fine pitch soldering) on their STAMP :-)

I think the bit bashed parallel interface will work, as my understanding is that the bandwidth is pretty low across this interface. It is just used for command and control. There are (just) enough PF pins to implement the interface.

The idea is that later on we can integrate the Blackfin and line interface hardware on one card. In that case the bit bashing will go away. Anyway, I would welcome any comments on the bit-bashed approach, or suggestions on other approaches.

The line side protection design is a mixture of the recommendations in the FALC56 data sheet and Jim "Dude" Dixons Quad primary rate card tormenta 2 design. The choice of matching resistors is a compromise between E1 and T1 (thanks to Jan Berger for this suggestion).

Status

The schematic/design is nearly complete, with a few tasks left to go before we can think about PCB layout. Below is a list of tasks required to complete the design in checklist form:

[ ] Explore clocking options and work out the best way to provide
    loop and master clocking.
[ ] Determine if Blackfin serial port can talk to the FALC56 using
    a zero glue logic design.  Draw a timing diagram.
[ ] Route all of the unused clocking pins and programmable pins
    to test points for easy access during debug.
[ ] Add three LEDS, probably drive off the general purpose XPn/RPn
    pins.  Might need buffers to handle the current.
[ ] Pass design rule check
[ ] Draw some figures illustrating the mechanical layout, connecting
    to PPI and SPORT0 on STAMP, and appropriate isolation gaps.

Please let me know if you would like to help with any of these tasks.

The schematics and have been drawn using the gschem program from the gEDA project. I must say the gschem is a really nice piece of software. Easy to use and works well. Well done gEDA team.

The 4fxo PCB has been designed using the PCB program, also part of the gEDA suite. I also used Perl and Makefiles to help generate the 4fxo PCB, as described here.

gEDA is an open source EDA suite that also includes simulation and PCB design tools. Seeing that we are developing GPL hardware it is nice to use open source tools where possible.

I downloaded the gEDA ISO and installed from CD. Install as a normal user (rather than root) as otherwise the installer breaks. You will be prompted for the root password several times as the installer proceeds. I found the tutorial a great way to learn gschem.

gEDA Hints

Buried in the gEDA install (/usr/local/bin/geda-install/share/pcb on my machine is a user guide for the PCB design package called pcb.pdf which is worth reading.

Don't put a "-" in any of the footprint names when using gschem or pcb, as this freaks out the m4 macros used when gsch2pcb to PCB is run. This actually managed to lock up my PC, not sure how but it was impressive!

Command line gsch2pcb -v -d pkg/newlib/ project to forward annotate sch to pcb.

perl -p -i.bak -e s/orginal/replacement/ *.sym is very useful for changing text inside the schematic or symbol files automatically.

The solder side of the PCB is used for the VCC and GND nets. Make sure you type j over any VCC tracks - this stops the polygon used for the GND net from overlapping the VCC track.

If you modify fxo.sch, perform a Design Rule Check (DRC) with:

gnetlist -g drc2 -o - sym/fxo.sch

To indicate success look for:

No warnings found.
No errors found.

Generate a new fxo netlist with:

[david@solomon hardware-0.2]$ gnetlist -g PCB -o sym/fxo.net sym/fxo.sch

Generate the 4fxo netlist with:

[david@solomon hardware-0.2]$ make net

The 4fxo PCB is generated using make and some perl scripts, using the process described here. To build the 4fxo PCB from the source files (for example after modifying fxo.pcb):

[david@solomon hardware-0.2]$ make pcb

You can directly edit 4fxo.pcb using the PCB GUI editor. To regenerate the fxdigital.pcb file after manual edits of 4fxo.pcb:

[david@solomon hardware-0.2]$ make fxdigital

This will ensure that the next make pcb includes the edits you have made using the GUI.

To check the complete PCB:

1. Start PCB pcb 4fxo.pcb&

2. Load the netlist "File - Load netlist file", select 4fxo.net

3. Type "o". You should get a dialog saying "Congratulations, the layout is complete and no shorted nets". This means the board is fully routed.

Then perform a Design Rule Check (DRC):

1. "Connects - Design Rule Checker". You should get a dialog saying "Congratulations….No DRC problems found".

If you need to update any footprints (especially if they are used many times), you might find the Perl script described here useful.

I found quite a lot of differences between footprints in the various PCB libraries, so I decided to create my own library of footprints. These are stored in bf-pkg/newlib. I then printed the footprints and checked their dimensions against the same packages on commercial PCBs.

Here are some references for the mechanical data:

1. DO-214AA, RV1 transient suppressor, www.teccor.com 6_MD_2.pdf, SIDACtor Device Handbook - Mechanical Data.

2. SOD-123, Z1 Zener, www.diodes.com ap02001.pdf

3. Two SOT-23 definitions, that have different distances to middle pin (2.0 and 2.3mm). So I made one footprint that can handle both, using an elongated pad for the central pin. SOT-23, Q1-Q5 Transistors, www.fairchildsemi.com MMBTA42.pdf, www.diodes.com ap02001.pdf data sheet.

4. TSSOP20 and TSSOP19, Si Chip set, Si3050/Si3019 Data Sheet.

5. 0603, 0805, 1206, 1206pol, 1210, 2010 were checked against the table in the "Creating Two Terminal SMD Devices" listing here.

6. RJ12 Altronics P1426 6 way 6 wire, Oupiin http://www.oupiin.com dimensions in catalog and Oupiin part number 8949-F, Oupiin data sheet A184.pdf

7. Oscillator module http://www.hy-q.com.au/oscillators/cus-intro.htm

here

Tar ball containing all schematic and PCB files: hardware-x.y.tar.gz

Schematics in PDF form: *.pdf